The invention relates to technology for designing and verifying an electronic design, such as the design of an integrated circuit (“IC”).
Modern electronic design is typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design and verification.
Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to test stimuli. For many types of designs, simulation can and should be performed during the design process to ensure that the ultimate goals are achievable and will be realized by the finished product. The exploding demand for high performance electronic products has increased interest in efficient and accurate simulation techniques for integrated circuits. For analog designs, an analog-based simulation approach such as SPICE is commonly used to implement simulation of the design. For digital circuit, equivalent digital simulation is performed.
With a growing complexity of System-On-A-Chip (SoC) designs, performing mixed-signal simulation has become a very critical aspect of design verification process. A mixed-signal design contains analog as well as digital blocks that interact with each other. The analog blocks require continuous time-domain (analog) simulators to compute their behavior while digital blocks rely on discrete time event driven (digital) simulators. A mixed-signal simulator uses both analog and digital simulation paradigms and performs the required inter-domain communication to simulate the interaction between analog and digital blocks. Such inter-domain communication is a very important component for controlling the accuracy and performance of the mixed-signal simulation. Hardware description languages, such as Verilog-AMS and VHDL-AMS, allow for effective modeling and simulation of mixed-signal designs.
One of the key challenges with mixed-signal verification is the ability to write testbenches which are scalable and reusable for both digital and mixed-signal verification. At the SoC level, the digital verification techniques are employed on the complete digital representation of the design. The testbenches created for verification “assume” the digital representation of the design. To gain more accuracy for certain sensitive design blocks, the abstraction level is switched from digital to analog/Spice. This leads to a “mixed-signal” design configuration that offers ability to perform more accurate mixed-signal verification. Such change in the design configuration essentially leads to a change in the design topology from simulation point of view and the interactions of various signals/blocks needs to be reconsidered.
To explain, consider the example design and testbench configuration for digital verification 102 and mixed-signal verification 104 illustrated in FIG. 1. In pure digital verification, the digital blocks (V1, V2, V3) are verified using a digital testbench, where the blocks V1, V2 and V3 are interconnected. The digital testbench communicates with signals, both within these blocks and between these blocks. As shown in this figure, the SPICE stimulus in digital testbench is not active in the pure digital verification mode.
When one of the digital blocks, e.g., V2, is replaced by a SPICE block such as S2, the design becomes a mixed-signal design. In this case, the user intention is that the digital testbench should continue to verify the digital parts of the design (V1, V3) and any digital signals that connect these blocks. In this configuration, the SPICE stimulus in the testbench block will become active and is used to directly communicate with the SPICE block S2. This communication is typically performed using real numbers to verify the analog block.
To accomplish this, one possible approach is to allow a conventional Verilog-AMS connect module to perform a translation between a digital representation and an analog representation at run-time. The problem with this approach is that this creates a performance penalty at run-time, which can cause delays and excessive resource consumption at the least opportune time. Moreover, requiring the conventional connect module to perform a translation fails to provide the flexibility to assign specific analog values to the translated signal, even if desired by the user.
Another possible approach involves rewriting portions of the testbench to work with the mixed-signal design configuration. While more flexible than the previously-described approach that performs run-time translation using a connect module, this approach is a highly manual process that needs to be executed every time the design configuration is changed to replace a digital representation with an analog representation. Such tight dependency of the testbench on the design configuration creates challenges for maintaining the testbench, is very error-prone, and could lead to significant productivity costs for verification engineers.
Therefore, there is a need for an improved approach to handle the different types of signal traffic for mixed-signal verification and simulation. Some embodiments of the invention address these issues by enabling development of highly effective and reusable testbenches in both pure digital and mixed-signal verification environment, involving the concept of hierarchical dual-value signals for mixed-signal simulation. Such dual-value signals can hold both analog and digital representations of a signal and use the appropriate representations based on which block (analog or digital) for which there is an interaction. Also described herein are simulation semantics that allow declaration, use and computation of such dual valued signals which also supports the ability to auto-select the appropriate signal value representation to eliminate the need for any analog-digital translations. For example, if a dual-value signal is interacting with analog block, the analog value representation is used. This eliminates the need for any analog-digital value conversion and offers direct controllability, observability and accuracy of simulation results. The use of dual-value signal enables very effective verification planning and helps in a tremendous savings in verification cost.
A significant advantage of this approach is that it provides the ability to drive and/or control an analog net segment from the digital testbench without affecting the other (digital) segments of the same signal. Moreover, it provides the ability to control analog nets in the design in this manner, while allowing the remaining analog and digital nets to communicate via standard mixed-signal semantics (e.g., as defined in the Verilog-AMS language). In addition, the effect of driving/controlling an analog net segment can be programmed directly from the digital testbench, which can better reflect the verification needs of the designer or engineer. This approach also allows the ability to reuse the same digital testbench for both digital and mixed-signal verification, irrespective of whether the testbench has some special stimulus for SPICE blocks (which may or may not be part of the design for a given simulation run).
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.